1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to an MRAM (Magnetic Random Access Memory).
2. Description of the Related Art
An MRAM is one of the nonvolatile semiconductor memories utilizing the tunneling magneto resistive effect to store information according to a variation in the resistance.
In order to read out data from the MRAM, a tunnel current which passes through a tunnel insulating film having a thickness of approximately several nanometers and provided between a free layer and a fixed layer is used. A value of the tunnel current is finely changed according to the thickness of the tunnel insulating film. Further, since the tunnel insulating film is made thin, there occurs a possibility that the tunnel insulating film will be inadvertently broken in the processing operation and the free layer and fixed layer will be short-circuited.
At the data write time, a magnetic field generated by a current running, nearby the MTJ is used. It is understood that the write characteristic greatly varies according to the shape of a magnetic body, for example, an MTJ (Magnetic Tunnel Junction) element contained in a memory cell. However, it is difficult to completely eliminate a variation in the shape of the MTJ element at the manufacturing time even in future. It is presumed that the operation of writing data into the memory cell cannot be performed when even a slight variation occurs in the shape of the MTJ element.
Under these circumstances, in the MRAM, there occurs a strong possibility that memory cells (faulty memory cells) having a characteristic significantly different from that defined in the specification at the write time and read time will be provided in a main memory cell array. Therefore, it is considered necessary to replace the above memory cells by redundant memory cells in order to enhance the manufacturing yield.
In a document 1, it is described that a write current for each line of WL, BL is approximately 5 mA. It is also difficult even in future to reduce the write current. One of the reasons is that the MTJ element becomes less resistant to thermal disturbance in a case where the MTJ element is designed to permit the write operation to be easily performed by use of a small current. Due to this, the advantage of the MRAM which can be used as the nonvolatile semiconductor memory will be lost in some cases.
Further, a demagnetizing field becomes stronger with miniaturization of the memory cells and, as a result, a switching magnetic field which is required to be applied to the MTJ from the exterior becomes stronger.
This means that the area of a current source which generates a write current, for example, the area occupied by a driver transistor becomes larger. In practice, it is desirable to suppress the ratio of the area of the driver transistor to the whole area of the chip to minimum.
On the other hand, the redundancy technique for replacing a faulty bit in the memory cell array by a normal bit includes the row redundancy technique for performing the replacement operation in the row unit and the column redundancy technique for performing the replacement operation in the column unit. In this specification, it is assumed that a redundant memory cell array for column redundant which is different from the main memory array is arranged in the chip. Further, it is assumed that a plurality of driver transistors used to supply write currents to write word lines of the main memory cells are commonly used in the main memory cell array and are connected to the write word lines by use of switches controlled by a decoder. According to the above method, since the driver transistors which require a large area can be arranged along the main memory array, the height of the memory cell array (the length of the memory cell array in the column direction) can be made small.
In this case, normally, since the size of the redundant memory cell array is smaller than the size of the main memory array, a region in which the driver transistors are arranged projects from the redundant memory cell array, for example, if the driver transistors are arranged in the redundant memory cell array in the same manner as in the main memory cell array. The layout thus attained acts against the intention of reducing the chip area.
Document 1: A. Bette et al., “A High-Speed 128 kbit MRAM Core for Future Universal Memory Applications” 2003 Symposium on VLSI Circuits Digest of Technical Papers, p. 217.